`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/09 08:57:11
// Design Name: 
// Module Name: counter_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module counter_sim();
    wire out;
    reg clk = 1;
    reg rst = 1;
    counter UUT(.clk_i(clk), .rst(rst), .out(out));
    
    always #1 begin clk=~clk; end
    initial begin
        #200 rst = 0;
        #400 rst = 1;
        #100000 $stop;
    end
endmodule
